1. Technical Field
The present disclosure relates to an electronic circuit having a digital-to analog conversion feedback loop and, more particularly, to a continuous time delta-sigma modulator (CTDSM) having a digital-to analog conversion feedback loop and an electronic circuit including the CTDSM.
2. Discussion of Related Art
A delta-sigma modulator (DSM) provides highly precise modulation with low noise, and is widely used in high-end audio systems, communication systems, and precise measuring devices.
FIG. 1 is a block diagram illustrating architecture of a general DSM.
Referring to FIG. 1, the CTDSM 10 includes an integrator 11, a quantizer 12, and a feedback digital-to-analog converter (DAC) 13. Input signal VIN may be a single-ended signal, or the input signal VIN may be a differential signal. An input resistor RIN may be included in the input stage. Architecture of the CTDSM may be modified according to an order of the CTDSM or the kind of input signal VIN.
A discrete time delta-sigma modulator (DTDSM) (not shown) has similar architecture to the CTDSM 10, and the DTDSM is widely used together with the CTDSM 10. An integrator (not shown) of the DTDSM receives a discrete input pulse, while the integrator 11 of the CTDSM 10 receives an analog input signal that continuously varies according to time.
The CTDSM 10 integrates the analog input signal and, thus, the CTDSM 10 may have less strict requirements, such as a settling time during which an output of an operational amplifier 111 in the integrator 11 is settled, than the DTDSM. In addition, the CTDSM 10 may not require an anti-aliasing filter, may be implemented with a lower order, and may consume less power compared with the DTDSM.
The integrator 11 integrates a sum of an input current IIN and an analog-converted feedback signal IF. The input current IIN corresponds to the input signal VIN divided by the input resistor RIN. The response characteristic of the CTDSM 10 is proportional to the linearity of the integrator 11. The integrator 11 is exemplified as an active RC configuration using the operational amplifier 111 and a capacitor CI.
The quantizer 12 quantizes an output of the integrator 11 and provides the quantized output as a digital output Q. The feedback DAC 13 receives the digital output Q and converts the digital output Q to the analog feedback signal IF. The analog-converted feedback signal IF is summed with the input current IIN at a summing node NSUM, and the summed signal is applied to the integrator 11.
The feedback DAC 13 may be implemented with various configurations, and the basic object of the feedback DAC 13 is to provide the analog feedback current IF corresponding to the digital output Q of the quantizer 12 to the summing node NSUM. The feedback DAC 13 may be implemented with a current DAC (I-DAC), or a switched capacitor DAC (SC-DAC). The I-DAC includes current sources, and provides analog current by combining outputs of the current sources. The SC-DAC includes current sources, switches, and a capacitor, and controls the analog current by providing charges, or being provided with charges, at every clock.
FIG. 2A is a block diagram illustrating the input part of the CTDSM in FIG. 1 in which the feedback DAC 13 in FIG. 1 is implemented with an I-DAC 13a. The input part includes the input resistor RIN, the integrator 11, and the feedback DAC 13. The feedback DAC 13 in FIG. 1 is implemented with the I-DAC 13a in FIG. 2A.
Referring to FIG. 2A, the I-DAC 13a includes first and second current sources 21 and 22. The first and second current sources 21 and 22 are respectively connected to or disconnected from the summing node NSUM by first and second switches S1 and S2 in response to the digital output Q of the quantizer 12. The I-DAC 13a provides the feedback current IF to the summing node NSUM during one cycle or a half cycle of the digital output Q according to the digital output Q.
FIG. 2B is a block diagram illustrating the input part of the CTDSM in FIG. 1, in which the feedback DAC 13 in FIG. 1 is implemented with the SC-DAC 13b. 
Referring to FIG. 2B, first, second, and third charging switches SC1, SC2 and SC3, and first and second discharging switches SD1 and SD2 are connected to first and second terminals of a switched capacitor CS. The first and the second charging switches SC1 and SC2 respectively connect first and second voltage sources 23 and 24 to the switched capacitor CS, and the third charging switch SC3 connects the switched capacitor CS to the summing node NSUM. The first and second discharging switches SD1 and SD2 are turned on in response to a first control signal φ1. The first charging switch SC1 or the second charging switch SC2 and the third charging switch SC3 are turned on in response to a second control signal φ2 according to the digital output Q, and the first voltage source 23 or the second voltage source 24 is connected to the summing node NSUM through the switched capacitor CS. When the first voltage source 23 or the second voltage source 24 is connected to the switched capacitor CS in response to the second control signal φ2, the switched capacitor CS is rapidly charged. Therefore, an impulse type current occurs in the initial charging operation.
The total amount of charges delivered to the integration capacitor CI is the same in both cases of FIGS. 2A and 2B, because an amount of charge corresponding to the digital output Q is delivered in both cases of FIGS. 2A and 2B.
FIG. 2C is a graph illustrating current variations with respect to time in the I-DAC of FIG. 2A and in the SC-DAC of FIG. 2B. Referring to FIG. 2C, the current of the I-DAC is relatively small and constant, while the current of the SC-DAC reaches its peak value initially and drops suddenly to reach its final value that is even smaller.
Because the current of the DAC 13 (I-DAC 13a or SC-DAC 13b) is applied to the integrator 111, the current of the DAC has a close relation with the current driving capability of the operational amplifier 111 included in the integrator 11. In the case of the I-DAC, a relatively small constant current is provided and, thus, the operational amplifier may have a low current driving capability and consumes a small amount of power in a real implementation. In the case of the SC-DAC, however, a large current is provided initially and, thus, the operational amplifier may have a large current driving capability and consumes a large amount power in a real implementation.
Noise, such as jitter, may occur in a clock signal for controlling the switches. In the case of the I-DAC 13a, constant current is provided at the latter part of the cycle of the digital output and, thus, positive charges proportional to the jitter are provided to increase an error due to the noise. On the other hand, in the case of the SC-DAC 13b, a very small current is provided at the latter part of the cycle of the digital output and, thus, the error may be insignificant despite the jitter.
As described above, when the feedback DAC 13 is implemented with the conventional the I-DAC 13a or the SC-DAC 13b, the CTDSM 10 is sensitive to jitter in the case of employing the I-DAC 13a for reducing power consumption, or the CTDSM consumes a large power in the case of employing the SC-DAC 13b that is robust to jitter.
For solving these problems, architecture that employs the SC-DAC and inserts a resistor between the switched capacitor and the summing node has been proposed. The proposed architecture, however, restricts not only the initial increasing of current but also the final decreasing of current and, thus, the CTDSM becomes sensitive to jitter.